1. Field of the Invention
The present invention relates to a technique in the field of liquid crystal displays (LCDs), and more particularly to a circuit and a method for driving LCDs.
2. Description of Related Art
In recent years, LCD televisions have been regarded as a future star of consuming electronic products. However, when R&D personnel are doing designs on the driving circuits of the panels of LCD televisions, they are inclined to proceed with the designs by relying on their experiences on the driving circuits of LCD panels, and this results in problems.
Regarding illustrations of the driving circuits of the conventional LCD televisions, FIG. 1 is a schematic view showing a panel module for a conventional LCD television, and FIG. 2 shows a sub-pixel of a conventional display panel.
As shown in FIG. 1, the panel module includes a control board 11, a front source board 121, a rear source board 122, a gate board 13, and a display panel 14. The control board 11 includes a timing controller 111 (TCON). A plurality of source driving units 151, 152 are disposed between the display panel 14 and the front source board 121, and between the display panel 14 and the rear source board 122. Each of the source driving units 151, 152 has a source driving IC (or so-called “data IC”, not shown). Further, a plurality of gate driving units 161, 162 are disposed between the display panel 14 and the gate board 13. Each of the gate driving units 161, 162 has a gate driving IC (or so-called “scan IC”, not shown).
The timing controller 111 on the control board 11 is employed for outputting controlling signals to the source driving ICs and the gate driving ICs so as to enable, row by row and in sequence, the thin-film transistors (TFTs) of the display panel 14, and to charge and discharge the liquid crystal capacitances to each required gray level. For example, as shown in FIG. 2, when the Y gate line is selected, the TFTs 21, 22 electrically connected to the Y gate line will be turned on, and thereafter the 1st to the N source driving ICs will output whole displayed data at one time (as a rule, an amplitude of an analogue voltage is revealed to show the amount of data) to the liquid crystal capacitances (Clc) 231, 232. By the storage capacitances (Cs) 241,242, the accuracy for all the data can be maintained until this gate line is selected again. When the Y+1 gate line is selected, the action mentioned above will be repeated, so that, by doing the actions in sequence, the actions to display a frame will be completed.
An example is made by a display panel complying with the wide extended graphics array+(WXGA+) and with 1366×768 resolution. Under the system signal specification defined by the National Television System(s) Committee (NTSC), 768 gate lines are required to transmit, in sequence, actuating signals during a frame time (about 16.67 ms) to turn on TFTs. In other words, every gate line can only have a share of 21.7 us (46.08 KHz). The effect of this is that during such a short period, there are a total number of 1366×3 TFTs needed to finish the actions of Turning On/Turning Off the gate, and further, the displayed data need to be written into the crystal capacitances of the source-drain. Besides, the above-mentioned short period does not include the blanking period outside the displaying area and the signal delay on the transmission lines.
It is understood that every gate line undergoes being enabled and disabled, in a very short period and with very rapid frequency. At the moment the gate line is enabled or disabled, the changing of the voltage is the most significant (about 30 to 40 volts), and then through a parasitic capacitance, Cgd, the voltage of display electrodes is affected.
The existence of the above-mentioned Cgd is similar to a common CMOS circuit wherein a parasitic capacitance is produced between the gate and the drain of a MOS. Because the gate on a display panel is connected to the outputting line of a source driving IC, in case the voltage on the source driving IC outputting line changes significantly, the voltage of the display electrodes is affected.
For example, when the gate line of a frame is enabled, an upward feed-through voltage will be produced to the displaying electrodes. However, for the sake of the enabling of the gate line at this time, the source driving IC will start to charge the display electrodes. As such, even though the voltage is not correct in the beginning due to the influence of the feed-through voltage, the source driving IC can charge the display electrodes to the correct voltage. The influence is not so large.
However, in the case where the gate line is enabled, since the source driving IC will no longer charge the display electrodes, the voltage droop (30-40 volts) produced by the disabling of the gate driving IC will feed through the displaying electrodes via the parasitic capacitance Cgd, resulting in a feed-through voltage drop on the displaying electrodes so as to affect the accuracy of the displayed grey level, and making a viewer senses the grey level discontinuity of a frame. Accordingly, in designing a driving circuit, special attention is required with respect to timing control and signal errors.
Currently, the primary issue encountered on designing display panels is the water waveform noise. When assembling an inverter of the system side to a display panel, the display frame will appear a horizontal water waveform noise. This is because in the inverter the lamp operation frequency and the horizontal synchronize (Hsync) frequency fail to synchronize with each other, and moreover, they interfere with each other, making the shared transient time for each gate line inconsistent with each other and causing a minor variation on the brightness of visual grey level.
Currently, solutions for the above-mentioned issue are:    1. Making the lamp operation frequency of the inverter as far away from the Hsync frequency as possible; and    2. Forcing the lamp operation frequency of the inverter to synchronize with the Hsync frequency so as to prevent interference from each other.
Regarding the first solution, since the two frequencies are away from each other in a limited range and besides, the Hsync frequency can be switched at the system terminal of a television, there still occurs a little water-like waveform noise. In other words, to maintain stability of the electric current of a cold cathode fluorescent lamp (CCFL), nowadays for most inverters the concept of constant current is adopted in designing a post-stage outputting circuit. Therefore, the range of the lamp operation frequency is limited by such parameters as, for example, feedback compensation value. Further, the signal standards can be switched from NTSC to Phase Alteration Line (PAL) or vice versa, so that the Hsync frequency can be varied and that the possible interference with the lamp operation frequency of the inverter is increased.
As to the second solution, using a complex programmable logic device (CPLD) is necessary so as to force the lamp operation frequency of the inverter to synchronize with the Hsync frequency. Nevertheless, such a solution not only raises the cost, but also causes a problem that there is a potential for the count of the timing clock will not be an integer during several frames.